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Our major IC design projects are:

 

Design of Receiver Chipset for PHS Phone


Two patents issued. This chipset has been designed for Japanese cordless phone

 

Design of Chipset for IF Section of DECT Receiver


his chipset has been used in mass production of Symbolic DECT mobile handsets.

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Design of Chipset for Digital AMPS Mobile Receiver


This chipset has been used in mass production of Ericsson mobile handset. The above figure shows the cover page of RF Design Magazine related to this chipset.

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Design of IF Section of GSM Transceiver Chipset


          

6 patents issued and chipset has been used in mass production of Fizz and Spare mobile handsets.

 

Design Chipset for DECT Handsets and Modules


Two patents issued. The chipset has been used in Siemens DECT handsets and Alps DECT Module.

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Design of 1V CMOS Pager Chipset


This chipset has been designed with 0.35 CMOS technology. The results have been two technical papers presented at IEEE IC design conferences.

 

 

Design of GPS RF IC


This chipset has been designed with TSMC 0.35um CMOS technology. This chip is interfaced with the Baseband unit that provides further processing on the signal.

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Design of GPS Baseband IC


Four patents issued. The baseband performance has been tested and approved by implementation on Altera FPGA circuits.

 

Wireless LAN IC Redesign


This IC has been mass-produced and used in 802.11b wireless LAN devices.

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Wireless LAN 802.11a IC Design


Four patents filed and the IC has been used in 802.11a WLAN equipment.

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Design of 10 Gbps ICs, Including Post Amplifier, Transimpedance Amplifier and Laser Diode Driver


Design of ICs in 0.13 um technology, several key patents filed.

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Redesign of GPS RF IC

This chip has low power consumption in comparison to the last sample and in accordance to its structure occupies a smaller place than the other one. This chip has the ability to change the signal path gain (VGA). This chipset has been designed with 0.35um CMOS technology.
This RF chip and a full Arm-based FPGA for Baseband have been developed. First full signal locked off the air was received in the first week of May 2004.

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Redesign of GPS Baseband IC


The target is to design and implement a GPS Baseband Processor on a FPGA. This FPGA has the ability to lock and extract the transmitted data from 12 satellites simultaneously. Low power consumption of this GPS makes it suitable for use in mobiles and hand watches. The design has standard AMBA buses so it can easily be used beside an ARM processor.

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RFID Tag IC And Module


             

The target of this project is to design and manufacture an RFID chip with average range of 10 meters and data rate of 50Kbps in the frequency of 2.4 GHz. This chipset has been designed with 0.18um CMOS technology.
This chip has the ability to receive energy from radiated RF signal, reading from and writing to EEPROM Anti Collision algorithm and is accessible to 70 units of seconds.
This chip works in two frequency modes: 2.4 MHz and 100 MHz and it can work in active and/or passive states.

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